As for specs, it is learned that each Xe-HP “tile” (a silicon die sub-unit that adds up in MCMs for higher tiers of Xe scalar processors), features 512 execution units (EUs). Compare this to the Xe-LP iGPU solution found in the upcoming “Tiger Lake” processor, which has 96. Intel has been able to design scalar processors with up to four tiles, adding up to 2,048 EUs. It remains to be seen if each tile on the scalar processors also include the raster hardware needed for the silicon to function as a GPU. The number of tiles on Xe-HPG are not known, but it reportedly features GDDR6 memory, and so the tile could be a variation of the Xe-HP. Intel SVP and technology head Raja Koduri is expected to detail the near-future of Intel architectures at a virtual event later today, and Xe-HPG is expected to come up.
Intel appears to have every intention of addressing the performance gaming segment with its Xe graphics architecture. According to information leaked to the web by VideoCardz, Xe-HPG (high performance gaming?) represents a product vertical dedicated to the gaming segment. Among the other verticals are Xe-HPC (high performance compute). The Xe-HPG graphics architecture is being developed for a 2021 market launch. It will feature all the client-segment staples, including a conventional PCI-Express interface, and GDDR6 memory instead of HBM. Intel may also eye DirectX 12 Ultimate logo compliance. Intel’s Xe discrete GPU and scalar processor development is already de-coupled with Intel’s foundry business development, and so the company could contract external foundries to manufacture these chips.